Cypress Semiconductor enCoRe CY7C601xx Guia do Utilizador descarregar pdf (Página 56)

CY7C601xx

CY7C602xx

Document 38-16016 Rev. *C Page 56 of 62

Figure 20. SPI Master Timing, CPHA = 1

Figure 21. SPI Slave Timing, CPHA = 1

MSB

T

MSU

LSB

T

MHD

T

SCKH

T

MDO

SS

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MISO

(SS is under firmware control in SPI Master mode)

T

SCKL

MSB LSB

MSB

T

SSU

LSB

T

SHD

T

SCKH

T

SDO

SS

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MISO

T

SCKL

T

SSS

T

SSH

MSB LSB

1 2 ... 51 52 53 54 55 56 57 58 59 60 61 62

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