Cypress Semiconductor CY14B101K Especificações descarregar pdf (Página 22)

CY14B101K

Document Number: 001-06401 Rev. *J Page 22 of 29

Hardware STORE Cycle

Parameter

Alt.

Parameter

Description

CY14B101K

Unit

Min Max

DELAY

[25]

Time Allowed to Complete SRAM Cycle 1 70 μs

PHSB

HLHX

Hardware STORE Pulse Width 15 ns

Figure 15. Hardware STORE Cycle

Soft Sequence Commands

Parameter Description

CY14B101K

Unit

Min Max

[22, 24]

Soft Sequence Processing Time 70 μs

Figure 16. Soft Sequence Processing

[22, 24]

+/+;

6725(

+/%/

'(/$<

'$7$9$/,'

+,*+,03('$1&(

+6%,1

'4'$7$287

+6%287

3+6%

$GGUHVV $GGUHVV $GGUHVV $GGUHVV

6RIW6HTXHQFH

&RPPDQG

$GGUHVV

6RIW6HTXHQFH

&RPPDQG

Notes

23. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

24. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See specific command.

25. Read and Write cycles in progress before HSB

are given this amount of time to complete.

Not Recommended for New Designs

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