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CY7C1361V25

CY7C1363V25

CY7C1365V25

PRELIMINARY

Functional Description

Single Read Accesses

This access is initiated when the following conditions are sat-

isfied at clock rise: (1) ADSP

or ADSC is asserted LOW, (2)

, CE

are all asserted active, and (3) the write signals

(GW

, BWE) are all deasserted HIGH. ADSP is ignored if CE

is HIGH. The address presented to the address inputs is

stored into the address advancement logic and the Address

input is asserted LOW, the requested data will be available at

the data outputs a maximum to t

CDV

after clock rise. ADSP is

ignored if CE

is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP

is asserted LOW, and (2)

, CE

are all asserted active. The address presented

is loaded into the address register and the address advance-

ment logic while being delivered to the RAM core. The write

signals (GW

, BWE, and BW

) and ADV inputs are ignored dur-

ing this first clock cycle. If the write inputs are asserted active

(see Write Cycle Descriptions table for appropriate states that

indicate a write) on the next clock rise, the appropriate data will

be latched and written into the device. The

CY7C1361V25/CY7C1365V25/CY7C1363V25 provides byte

write capability that is described in the Write Cycle Description

table. Asserting the Byte Write Enable input (BWE

) with the

selected Byte Write (BW

a,b,c,d

for CY7C1361V25/

CY7C1365V25 and BW

a,b

for CY7C1363V25) input will selec-

tively write to only the desired bytes. Bytes not selected during

a byte write operation will remain unaltered. All I/Os are three-

stated during a byte write.

Because the CY7C1361V25/CY7C1365V25/CY7C1363V25

is a common I/O device, the Output Enable (OE

) must be

deasserted HIGH before presenting data to the DQ

inputs.

Doing so will three-state the output drivers. As a safety pre-

caution, DQ

are automatically three-stated whenever a write

cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) CE

, CE

are all asserted active,

and (4) the appropriate combination of the write inputs (GW

BWE

, and BW

) are asserted active to conduct a write to the

desired byte(s). ADSC

is ignored if ADSP is active LOW.

The address presented to A

[18:0]

is loaded into the address

ered to the RAM core. The ADV

input is ignored during this

cycle. If a global write is conducted, the data presented to the

is written into the corresponding address location in the

RAM core. If a byte write is conducted, only the selected bytes

are written. Bytes not selected during a byte write operation

will remain unaltered. All I/Os are three-stated during a byte

write.

Because the CY7C1361V25/CY7C1365V25/CYC7C1363V25

is a common I/O device, the Output Enable (OE

) must be

deasserted HIGH before presenting data to the DQ

inputs.

Doing so will three-state the output drivers. As a safety pre-

caution, DQ

are automatically three-stated whenever a write

cycle is detected, regardless of the state of OE.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register

that is triggered by the rising edge of CLK. As outputs, they deliver the data

contained in the memory location specified by A during the previous clock rise

of the read cycle. The direction of the pins is controlled by OE

. When OE is

asserted LOW, the pins behave as outputs. When HIGH, DQ

–DQ

and

–DP

are placed in a three-state condition.

TDO JTAG Serial

Output,

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

TDI JTAG Serial

Input,

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

TMS Test Mode Select,

Synchronous

This pin controls the Test Access Port state machine. Sampled on the rising

edge of TCK.

TCK JTAG-Clock Clock input to the JTAG circuitry.

Power Supply Power supply inputs to the core of the device. Should be connected to 2.5V

power supply.

Ground Ground for the device. Should be connected to ground of the system.

DDQ

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 2.5V power supply.

NC - No Connects.

DNU Do Not Use Pins. These pins should be left floating.

Pin Definitions (119-Ball BGA)

(continued)

Name I/O Description

1 2 3 4 5 6 7 8 9 10 11 12 ... 29 30

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