Cypress Semiconductor CY7C1365C Manual do Utilizador descarregar pdf (Página 22)

CY7C1361V25

CY7C1363V25

CY7C1365V25

PRELIMINARY

Timing Diagrams

Write Cycle Timing

[16, 17]

Notes:

16. WE is the combination of BWE, BW

and GW to define a write cycle (see Write Cycle Description table).

17. WDx stands for Write Data to Address X.

ADSP

CLK

ADSC

ADV

ADD

Data-

CYC

ADS

ADH

ADS

ADH

ADVS

ADVH

WD1

WD2

WD3

CES

CEH

CES

CEH

CES

CEH

Single Write

Burst Write

Unselected

ADSP

ignored with CE

inactive

masks ADSP

= DON’T CARE

= UNDEFINED

Pipelined Write

High-Z

Unselected with CE

ADV Must Be Inactive for ADSP Write

ADSC initiated write

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 28 29 30

CY7C1361V25 1
CY7C1363V25 1
CY7C1365V25 1
CY7C1361V25 10
PRELIMINARY 10
Revision History 30

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