Cypress Semiconductor Perform nvSRAM Especificações descarregar pdf (Página 21)

CY14B256KA

Document Number: 001-55720 Rev. *H Page 21 of 28

AutoStore/Power-Up RECALL

Over the Operating Range

Parameter Description Min Max Unit

HRECALL

[29]

Power-Up RECALL duration – 20 ms

STORE

[30]

STORE cycle duration – 8 ms

DELAY

[31]

Time allowed to complete SRAM write cycle – 25 ns

SWITCH

Low voltage trigger level – 2.65 V

VCCRISE

[32]

rise time 150 – µs

HDIS

[32]

HSB output disable voltage – 1.9 V

LZHSB

[32]

HSB to output active time – 5 µs

HHHD

[32]

HSB high active time – 500 ns

Switching Waveforms

Figure 12. AutoStore or Power-Up RECALL

[33]

SWITCH

HDIS

VCCRISE

STORE

HHHD

DELAY

LZHSB

HRECALL

HSB OUT

AutoStore

POWER-

RECALL

Read & Write

Inhibited

(RWI)

POWER-UP

RECALL

Read & Write

BROWN

OUT

AutoStore

POWER-UP

RECALL

Read & Write

POWER

DOWN

AutoStore

Note

Notes

29. t

HRECALL

starts from the time V

rises above V

SWITCH

30. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place

31. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t

DELAY

32. These parameters are guaranteed by design and are not tested.

33. Read and Write cycles are ignored during STORE, RECALL, and while V

is below V

SWITCH

34. During power-up and power-down, HSB

glitches when HSB pin is pulled up through an external resistor.

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