Cypress Semiconductor Perform nvSRAM Especificações descarregar pdf (Página 19)

CY14B256KA

Document Number: 001-55720 Rev. *H Page 19 of 28

AC Switching Characteristics

Over the Operating Range

Parameters

[18]

Description

25 ns 45 ns

Unit

Cypress

Parameter

Alt Parameter Min Max Min Max

SRAM Read Cycle

ACE

ACS

Chip enable access time – 25 – 45 ns

[19]

Read cycle time 25 – 45 – ns

[20]

Address access time – 25 – 45 ns

DOE

Output enable to data valid – 12 – 20 ns

OHA

[20]

Output hold after address change 3 – 3 – ns

LZCE

[21, 22]

Chip enable to output active 3 – 3 – ns

HZCE

[21, 22]

Chip disable to output Inactive – 10 – 15 ns

LZOE

[21, 22]

OLZ

Output enable to output active 0 – 0 – ns

HZOE

[21, 22]

OHZ

Output disable to output inactive – 10 – 15 ns

[21]

Chip enable to power active 0 – 0 – ns

[21]

Chip disable to power standby – 25 – 45 ns

SRAM Write Cycle

Write cycle time 25 – 45 – ns

PWE

Write pulse width 20 – 30 – ns

SCE

Chip enable to end of write 20 – 30 – ns

Data setup to end of write 10 – 15 – ns

Data hold after end of write 0 – 0 – ns

Address setup to end of write 20 – 30 – ns

Address setup to start of write 0 – 0 – ns

Address hold after end of write 0 – 0 – ns

HZWE

[21, 22, 23]

Write enable to output disable – 10 – 15 ns

LZWE

[21, 22]

Output active after end of write 3 – 3 – ns

Switching Waveforms

Figure 8. SRAM Read Cycle #1 (Address Controlled)

[19, 20, 24]

Address

Data Output

Address Valid

Previous Data Valid

Output Data Valid

OHA

Notes

18. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V

/2, input pulse levels of 0 to V

CC(typ)

, and output loading of the specified

and load capacitance shown in Figure 7 on page 18.

19. WE

must be HIGH during SRAM read cycles.

20. Device is continuously selected with CE

and OE LOW.

21. These parameters are guaranteed by design and are not tested.

22. Measured ±200 mV from steady state output voltage.

23. If WE

is low when CE goes low, the outputs remain in the high impedance state.

24. HSB

must remain HIGH during Read and Write cycles.

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