Document Number : 38-16007 Rev. *L Page 18 of 34
Table 19. Threshold Low
Addr: 0x19 REG_THRESHOLD_L Default: 0x08
76543210
Reserved Threshold Low
Bit Name Description
7 Reserved This bit is reserved and should be written with zero.
6:0 Threshold Low The Threshold Low value is used to determine the number of missed chips allowed when attempting to
correlate a single data bit of value ‘0’. A perfect reception of a data bit of ‘0’ with a 64 chips/bit PN code would
result in zero correlation matches, meaning the exact inverse of the PN code has been received. By setting
the Threshold Low value to 0x08 for example, up to eight chips can be erroneous while still identifying the
value of the received data bit. This value along with the Threshold High value determine the correlator count
values for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the receiver to
interference and the dependability of the received data. By allowing a minimal number of erroneous chips
the dependability of the received data increases while the robustness to interference decreases. On the
other hand increasing the maximum number of missed chips means reduced data integrity but increased
robustness to interference and increased range.
Table 20. Threshold High
Addr: 0x1A REG_THRESHOLD_H Default: 0x38
76543210
Reserved Threshold High
Bit Name Description
7 Reserved This bit is reserved and should be written with zero.
6:0 Threshold High The Threshold High value is used to determine the number of matched chips allowed when attempting to
correlate a single data bit of value ‘1’. A perfect reception of a data bit of ‘1’ with a 64 chips/bit or a 32 chips/bit
PN code would result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was
received perfectly. By setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be
erroneous while still identifying the value of the received data bit. This value along with the Threshold Low
value determine the correlator count values for logic ‘1’ and logic ‘0’. The threshold values used determine
the sensitivity of the receiver to interference and the dependability of the received data. By allowing a minimal
number of erroneous chips the dependability of the received data increases while the robustness to inter-
ference decreases. On the other hand increasing the maximum number of missed chips means reduced
data integrity but increased robustness to interference and increased range.
Table 21. Wake Enable
Addr: 0x1C REG_WAKE_EN Default: 0x00
76543210
Reserved Wakeup
Enable
Bit Name Description
7:1 Reserved These bits are reserved and should be written with zeroes.
0 Wakeup Enable Wakeup interrupt enable.
0 = disabled
1 = enabled
A wakeup event is triggered when the PD
pin is deasserted and once the IC is ready to receive SPI commu-
nications.
Not Recommended for New Designs
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