Document Number : 38-16007 Rev. *L Page 11 of 34
Table 8. SERDES Control
Addr: 0x06 REG_SERDES_CTL Default: 0x03
76543210
Reserved SERDES
Enable
EOF Length
Bit Name Description
7:4 Reserved These bits are reserved and should be written with zeroes.
3 SERDES
Enable
The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode.
1 = SERDES enabled.
0 = SERDES disabled, bit-serial mode enabled.
When the SERDES is enabled data can be written to and read from the IC one byte at a time, through the
use of the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through
the use of the DIO/DIOVAL pins, refer to section 3.2. It is recommended that SERDES mode be used to
avoid the need to manage the timing required by the bit-serial mode.
2:0 EOF Length The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap
without valid data before an EOF event will be generated. When in receive mode and a valid bit has been
received the EOF event can then be identified by the number of bit times that expire without correlating any
new data. The EOF event causes data to be moved to the proper SERDES Data Register and can also be
used to generate interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a
valid reception.
Table 9. Receive SERDES Interrupt Enable
Addr: 0x07 REG_RX_INT_EN Default: 0x00
76543210
Underflow B Overflow B EOF B Full B Underflow A Overflow A EOF A Full A
Bit Name Description
7 Underflow B The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive
SERDES Data B register (Reg 0x0B)
1 = Underflow B interrupt enabled for Receive SERDES Data B
0 = Underflow B interrupt disabled for Receive SERDES Data B
An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when
it is empty.
6 Overflow B The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive
SERDES Data B register (Reg 0x0B)
1 = Overflow B interrupt enabled for Receive SERDES Data B
0 = Overflow B interrupt disabled for Receive SERDES Data B
An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg
0x0B) before the prior data is read out.
5 EOF B The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition.
1 = EOF B interrupt enabled for Channel B Receiver.
0 = EOF B interrupt disabled for Channel B Receiver.
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit
has been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field.
If 0 is the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is
cleared by reading the receive status register
4 Full B The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B)
having data placed in it.
1 = Full B interrupt enabled for Receive SERDES Data B
0 = Full B interrupt disabled for Receive SERDES Data B
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data
B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether
or not a complete byte has been received.
Not Recommended for New Designs
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