CY7C1381D
CY7C1383D
Document #: 38-05544 Rev. *C Page 8 of 29
order. Leaving MODE unconnected will cause the device to
default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, CE
3
[2]
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
Sleep mode standby current ZZ > V
DD
– 0.2V 80 mA
t
ZZS
Device operation to ZZ ZZ > V
DD
– 0.2V 2t
CYC
ns
t
ZZREC
ZZ recovery time ZZ < 0.2V 2t
CYC
ns
t
ZZI
ZZ active to sleep current This parameter is sampled 2t
CYC
ns
t
RZZI
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
Truth Table
[3, 4, 5, 6, 7]
Cycle Description
ADDRESS
Used CE
1
CE
2
CE
3
ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle,
Power-down
None H X X L X L X X X L-H Tri-State
Deselected Cycle,
Power-down
None L L X L L X X X X L-H Tri-State
Deselected Cycle,
Power-down
None L X H L L X X X X L-H Tri-State
Deselected Cycle,
Power-down
None L L X L H L X X X L-H Tri-State
Deselected Cycle,
Power-down
None X X X L H L X X X L-H Tri-State
Sleep Mode, Power-down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE
= L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the
OE
signal.
OE
is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP
is asserted, regardless of the state of GW, BWE, or BW
X
. Writes may occur only on subsequent clocks
after the
ADSP
or with the assertion of
ADSC
. As a result,
OE
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
OE
is a
don't care for the remainder of the write cycle.
7.
OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when
OE
is
inactive or when the device is deselected, and all data bits behave as output when
OE
is active (LOW).
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