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CY7C1381D

CY7C1383D

Document #: 38-05544 Rev. *C Page 29 of 29

Document History Page

Document Title: CY7C1381D/CY7C1383D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Document Number: 38-05544

REV. ECN NO. Issue Date

Orig. of

Change Description of Change

** 254518 See ECN RKF New data sheet

*A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

non-compliance with 1149.1

Removed 117-MHz Speed Bin

Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA

package

Added comment of ‘Lead-free BG packages availability’ below the Ordering

Information

*B 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as

per JEDEC standard

Added description on EXTEST Output Bus Tri-State

Changed description on the Tap Instruction Set Overview and Extest

Changed Device Width (23:18) for 119-BGA from 000001 to 101001

Added separate row for 165 -FBGA Device Width (23:18)

Changed Θ

and Θ

for TQFP Package

from 31 and 6 °C/W to 28.66 and

4.08 °C/W respectively

Changed Θ

and Θ

for BGA Package

from 45 and 7 °C/W to 23.8 and 6.2

°C/W respectively

Changed Θ

and Θ

for FBGA Package

from 46 and 3 °C/W to 20.7 and

4.0 °C/W respectively

Modified V

OL,

test conditions

Removed comment of ‘Lead-free BG packages availability’ below the

Ordering Information

Updated Ordering Information Table

Changed from Preliminary to Final

*C 351895 See ECN PCI Updated Ordering Information Table

1 2 ... 24 25 26 27 28 29

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