Cypress Semiconductor CY7C1383D Manual do Utilizador descarregar pdf (Página 23)

CY7C1381D

CY7C1383D

Document #: 38-05544 Rev. *C Page 23 of 29

Write Cycle Timing

[25, 26]

Note:

26.

Full width write can be initiated by either GW

LOW; or by GW HIGH, BWE LOW and BW

LOW.

Timing Diagrams (continued)

CYC

CLK

ADH

ADS

ADDRESS

CEH

CES

High-Z

BURST READ BURST WRITE

D(A2)

D(A2 + 1)

D(A1)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

ADH

ADS

ADH

ADS

OEHZ

ADVH

ADVS

WEH

WES

WEH

WES

Byte write signals are ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

ADSP

ADSC

BWE,

ADV

Data in (D)

ata Out (Q)

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 29

CY7C1381D 1
CY7C1383D 1
Pin Configurations 3
165-ball fBGA (3 Chip Enable) 5
TAP Controller State Diagram 10
Truth Table for Read/Write 10

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