Cypress Semiconductor FX2LP Manual do Utilizador descarregar pdf (Página 33)

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Document #: 38-08032 Rev. *K Page 33 of 60

reserved

E6D2 1 EP2GPIFFLGSEL

[11]

Endpoint 2 GPIF Flag

select

0 0 0 0 0 0 FS1 FS0 00000000 RW

E6D3 1 EP2GPIFPFSTOP Endpoint 2 GPIF stop

transaction on prog. flag

0 0 0 0 0 0 0 FIFO2FLAG 00000000 RW

E6D4 1 EP2GPIFTRIG

[11]

Endpoint 2 GPIF Trigger x x x x x x x x xxxxxxxx W

3 reserved

reserved

E6DA 1 EP4GPIFFLGSEL

[11]

Endpoint 4 GPIF Flag

select

0 0 0 0 0 0 FS1 FS0 00000000 RW

E6DB 1 EP4GPIFPFSTOP Endpoint 4 GPIF stop

transaction on GPIF Flag

0 0 0 0 0 0 0 FIFO4FLAG 00000000 RW

E6DC 1 EP4GPIFTRIG

[11]

Endpoint 4 GPIF Trigger x x x x x x x x xxxxxxxx W

3 reserved

reserved

E6E2 1 EP6GPIFFLGSEL

[11]

Endpoint 6 GPIF Flag

select

0 0 0 0 0 0 FS1 FS0 00000000 RW

E6E3 1 EP6GPIFPFSTOP Endpoint 6 GPIF stop

transaction on prog. flag

0 0 0 0 0 0 0 FIFO6FLAG 00000000 RW

E6E4 1 EP6GPIFTRIG

[11]

Endpoint 6 GPIF Trigger x x x x x x x x xxxxxxxx W

3 reserved

reserved

E6EA 1 EP8GPIFFLGSEL

[11]

Endpoint 8 GPIF Flag

select

0 0 0 0 0 0 FS1 FS0 00000000 RW

E6EB 1 EP8GPIFPFSTOP Endpoint 8 GPIF stop

transaction on prog. flag

0 0 0 0 0 0 0 FIFO8FLAG 00000000 RW

E6EC 1 EP8GPIFTRIG

[11]

Endpoint 8 GPIF Trigger x x x x x x x x xxxxxxxx W

3 reserved

E6F0 1 XGPIFSGLDATH GPIF Data H

(16-bit mode only)

D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW

E6F1 1 XGPIFSGLDATLX Read/Write GPIF Data L &

trigger transaction

D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW

E6F2 1 XGPIFSGLDATL-

NOX

Read GPIF Data L, no

transaction trigger

D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R

E6F3 1 GPIFREADYCFG Internal RDY, Sync/Async,

RDY pin states

INTRDY SAS TCXRDY5 0 0 0 0 0 00000000 bbbrrrrr

E6F4 1 GPIFREADYSTAT GPIF Ready Status 0 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 00xxxxxx R

E6F5 1 GPIFABORT Abort GPIF Waveforms x x x x x x x x xxxxxxxx W

E6F6 2 reserved

ENDPOINT BUFFERS

E740 64 EP0BUF EP0-IN/-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW

E780 64 EP10UTBUF EP1-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW

E7C0 64 EP1INBUF EP1-IN buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW

E800 2048 reserved RW

F000 1024 EP2FIFOBUF 512/1024-byte EP 2 /

slave FIFO buffer (IN or

OUT)

D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW

F400 512 EP4FIFOBUF 512 byte EP 4 / slave FIFO

buffer (IN or OUT)

D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW

F600 512 reserved

F800 1024 EP6FIFOBUF 512/1024-byte EP 6 /

slave FIFO buffer (IN or

OUT)

D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW

FC00 512 EP8FIFOBUF 512 byte EP 8 / slave FIFO

buffer (IN or OUT)

D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW

FE00 512 reserved

xxxx I²C Configuration Byte 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx

[14]

n/a

Special Function Registers (SFRs)

80 1 IOA

[13]

Port A (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW

81 1 SP Stack Pointer D7 D6 D5 D4 D3 D2 D1 D0 00000111 RW

82 1 DPL0 Data Pointer 0 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW

83 1 DPH0 Data Pointer 0 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW

84 1 DPL1

[13]

Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW

85 1 DPH1

[13]

Data Pointer 1 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW

86 1 DPS

[13]

Data Pointer 0/1 select 0 0 0 0 0 0 0 SEL 00000000 RW

87 1 PCON Power Control SMOD0 x 1 1 x x x IDLE 00110000 RW

Notes:

13. SFRs not part of the standard 8051 architecture.

14. If no EEPROM is detected by the SIE then the default is 00000000.

Table 5-1. FX2LP Register Summary (continued)

Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 59 60

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