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Cypress Semiconductor Corporation

SL811HS and SL811HST: Application Notes

and specifications contained in this document are subject to change without

notice.

Date: 07/26/01

Revision: 1.21

Page: 18

3.3.2 Memory Buffer

The SL81HS Memory buffer is located between address 0x10 and 0xFF inclusive, and is used

for data buffering. The following Tables show Register labels and variables mapped to specific

memory and register locations that are used in the example code.

Table 4: DATA0/DATA1 Mapping

cMemStart 0x10

Host Memory Start

ubufA 0x80

Buffer A address for DATA0

ubufB 0xc0 Buffer B address for DATA1

uxferLen 0x40 Xfer Length

sMemSize 0xc0 Total SL811HS memory size

cMemEnd 256 Upper limit of memory

Table 5: Buffers use for configuration and Vendor Specific command

Value

EP0Buf 0x40

Endpoint 0 Buffer where SL811HS memory starts

EP0Len 0x40 Length of config buffer EP0Buf

Table 6: SL811HS Code Bit Definitions

Name Value Description

DATA0_WR 0x07 Arm+Enable+tranmist to Host+DATA0

DATA1_WR 0x05 Arm+Enable+tranmist to Host on DATA1

ZDATA0_WR 0x47 Arm+Transaction Ignored+tranmist to Host+DATA0

ZDATA1_WR 0x45 Arm+Transaction Ignored+tranmist to Host+DATA1

DATA0_RD 0x03 Arm+Enable+received from Host+DATA0

DATA1_RD 0x43 Arm+Enable+received from Host+DATA1

PID_SOF 0xa5 SOF Token

PID_SETUP 0x2d SETUP Token

PID_IN 0x69 IN Token

PID_OUT 0xe1 OUT Token

PID_PRE 0x3c PRE Token

PID_NAK 0x5a NAK Token

PID_STALL 0x1e STALL Token

PID_DATA0 0xc3 DATA0 Token

PID_DATA1 0X4b DATA1 Token

MAX_RETRY 0xffff Number of Re-try

TIMEOUT 6000L Time out

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 42 43

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