Cypress Semiconductor FLEx36 CY7C0850AV Manual do Utilizador descarregar pdf (Página 15)

CY7C0850AV,CY7C0851V/CY7C0851AV

CY7C0852V/CY7C0852AV

CY7C0853V/CY7C0853AV

Document #: 38-06070 Rev. *K Page 15 of 36

Figure 6. AC Test Load and Waveforms

Switching Characteristics

Over the Operating Range

Parameter Description

-167 -133 -100

Unit

CY7C0850AV

CY7C0851V/AV

CY7C0852V/AV

CY7C0850AV

CY7C0851V/AV

CY7C0852V/AV

CY7C0853V

CY7C0853AV

CY7C0853V

CY7C0853AV

Min Max Min Max Min Max Min Max

MAX2

Maximum operating frequency – 167 – 133 – 133 – 100 MHz

CYC2

Clock cycle time 6.0 – 7.5 – 7.5 – 10.0 – ns

CH2

Clock HIGH time 2.7–3.0–3.0–4.0–ns

CL2

Clock LOW time 2.7 – 3.0 – 3.0 – 4.0 – ns

[23]

Clock rise time – 2.0 – 2.0 – 2.0 – 3.0 ns

[23]

Clock fall time – 2.0 – 2.0 – 2.0 – 3.0 ns

Address setuptime 2.3 – 2.5 – 2.5 – 3.0 – ns

Address hold time 0.6 – 0.6 – 0.6 – 0.6 – ns

Byte select setup time 2.3 – 2.5 – 2.5 – 3.0 – ns

Byte select hold time 0.6 – 0.6 – 0.6 – 0.6 – ns

Chip enable setup time 2.3 – 2.5 – NA – NA – ns

Chip enable hold time 0.6 – 0.6 – NA – NA – ns

R/W setup time 2.3 – 2.5 – 2.5 – 3.0 – ns

R/W hold time 0.6 – 0.6 – 0.6 – 0.6 – ns

Input data setup time 2.3 – 2.5 – 2.5 – 3.0 – ns

Input data hold time 0.6 – 0.6 – 0.6 – 0.6 – ns

SAD

ADS setup time 2.3 – 2.5 – NA – NA – ns

HAD

ADS hold time 0.6 – 0.6 – NA – NA – ns

SCN

CNTEN setup time 2.3 – 2.5 – NA – NA – ns

HCN

CNTEN hold time 0.6 – 0.6 – NA – NA – ns

SRST

CNTRST setup time 2.3 – 2.5 – NA – NA – ns

HRST

CNTRST hold time 0.6 – 0.6 – NA – NA – ns

SCM

CNT/MSK setup time 2.3 – 2.5 – NA – NA – ns

HCM

CNT/MSK hold time 0.6 – 0.6 – NA – NA – ns

R1 = 590 

R2 = 435 

C = 5 pF

(b) Three-state Delay (Load 2)

90%

10%

3.0 V

90%

10%

<2ns <2ns

ALL INPUT PULSES

3.3 V

= 1.5 V

R = 50 

= 50

(a) Normal Load (Load 1)

C = 10 pF

OUTPUT

Note

23. Except JTAG signals (t

and t

< 10 ns [max.]).

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 35 36

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