Cypress Semiconductor CYS25G0101DX-ATC Manual do Utilizador descarregar pdf (Página 3)

CYS25G0101DX

Document Number: 38-02009 Rev. *K Page 3 of 17

Clocking

The source clock for the transmit data path is selectable from either the recovered clock or an external BITS (Building Integrated

Timing Source) reference clock. The low jitter of the CDR PLL allows loop timed operation of the transmit data path meeting all Bellcore

and ITU jitter requirements.

Multiple loopback and loop through modes are available for both diagnostic and normal operation. For systems containing redundant

SONET rings that are maintained in standby, the CYS25G0101DX may also be dynamically powered down to conserve system power.

SONET Data

Serial Data

Optical

XCVR

RD+

RD–

TD–

TD+

IN+

IN–

OUT–

OUT+

Serial Data

CYS25G0101DX

BITS Time

Reference

155.52 MHz

REFCLK

TXD[15:0]

TXCLKI

FIFO_ERR

TXCLKO

RXD[15:0]

RXCLK

LOOPTIME

DIAGLOOP

LOOPA

LINELOOP

RESET

PWRDN

LOCKREF

LFI

Processor

Transmit Data

Interface

Receive Data

Interface

Data & Clock

Direction

Control

Status and

System

Control

Host Bus

Interface

System or Telco Bus

Optical

Fiber Links

FIFO_RST

Figure 1. CYS25G0101DX System Connections

1 2 3 4 5 6 7 8 ... 16 17

SONET OC-48 Transceiver 1
CYS25G0101DX 10

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