Cypress Semiconductor CYDC128B16 Manual do Utilizador descarregar pdf (Página 16)

CYDC128B16

Document #: 001-01638 Rev. *H Page 16 of 29

Switching Characteristics for V

= 2.5 V Over the Operating Range

Parameter Description

CYDC128B16 CYDC128B16

Unit-40 -55

Min Max Min Max

Read Cycle

Read cycle time 40 55 ns

Address to data valid 40 55 ns

OHA

Output hold from address change 5 5 ns

ACE

[1]

CE LOW to data valid 40 55 ns

DOE

OE LOW to data valid 25 30 ns

LZOE

[2, 3, 4]

OE LOW to low Z 2 2 ns

HZOE

[2, 3, 4]

OE HIGH to high Z 15 15 ns

LZCE

[2, 3, 4]

CE LOW to low Z 2 2 ns

HZCE

[2, 3, 4]

CE HIGH to high Z 15 15 ns

[4]

CE LOW to power up 0 0 ns

[4]

CE HIGH to power down 40 55 ns

ABE

[1]

Byte enable access time 40 55 ns

Write Cycle

Write cycle time 40 55 ns

SCE

[1]

CE LOW to write end 30 45 ns

Address valid to write end 30 45 ns

Address hold from write end 0 0 ns

[1]

Address setup to write start 0 0 ns

PWE

Write pulse width 25 40 ns

Data setup to write end 20 30 ns

Data hold from write end 0 0 ns

HZWE

[3, 4]

R/W LOW to high Z 15 25 ns

LZWE

[3, 4]

R/W HIGH to low Z 0 0 ns

WDD

[5]

Write pulse to data delay 55 80 ns

DDD

[5]

Write data valid to read data valid 55 80 ns

Busy Timing

[6]

BLA

BUSY LOW from address match 30 45 ns

BHA

BUSY HIGH from address mismatch 30 45 ns

BLC

BUSY LOW from CE LOW 30 45 ns

BHC

BUSY HIGH from CE HIGH 30 45 ns

[7]

Port set up for priority 5 5 ns

R/W HIGH after BUSY (Slave) 0 0 ns

R/W HIGH after BUSY HIGH (Slave) 20 35 ns

BDD

[8]

BUSY HIGH to data valid 30 40 ns

Interrupt Timing

[6]

INS

INT set time 35 45 ns

[+] Feedback

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 29 30

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