Cypress Semiconductor CYDC128B16 Manual do Utilizador Página 1

CYDC128B161.8 V 4 K/8 K/16 K × 16 and 8 K/16 K × 8 ConsuMoBL Dual-Port Static RAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, C

CYDC128B16Document #: 001-01638 Rev. *H Page 10 of 29Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These user gu

CYDC128B16Document #: 001-01638 Rev. *H Page 11 of 29IIXInput leakage current 1.8 V 1.8 V –1 1 –1 1 μA2.5 V 2.5 V –1 1 –1 1 μA3.0 V 3.0 V –1 1 –1 1

CYDC128B16Document #: 001-01638 Rev. *H Page 12 of 29Electrical Characteristics for VCC = 2.5 V Over the Operating RangeParameter DescriptionCYDC128

CYDC128B16Document #: 001-01638 Rev. *H Page 13 of 29 ]Electrical Characteristics for 3.0 V Over the Operating RangeParameter DescriptionCYDC128B16

CYDC128B16Document #: 001-01638 Rev. *H Page 14 of 297Figure 2. AC Test Loads and WaveformsSwitching Characteristics for VCC = 1.8VOver the Operatin

CYDC128B16Document #: 001-01638 Rev. *H Page 15 of 29 tLZWE[4, 5]R/W HIGH to Low Z 0 0 nstWDD[6]Write pulse to data delay 55 80 nstDDD[6]Write data

CYDC128B16Document #: 001-01638 Rev. *H Page 16 of 29Switching Characteristics for VCC = 2.5 V Over the Operating RangeParameter DescriptionCYDC128B

CYDC128B16Document #: 001-01638 Rev. *H Page 17 of 29tINRINT reset time 35 45 nsSemaphore TimingtSOPSEM flag update pulse (OE or SEM)10 15 nstSWRDSE

CYDC128B16Document #: 001-01638 Rev. *H Page 18 of 29tHDData hold from write end 0 0 nstHZWE[3, 4]R/W LOW to high Z 15 25 nstLZWE[3, 4]R/W HIGH to l

CYDC128B16Document #: 001-01638 Rev. *H Page 19 of 29Switching WaveformsFigure 3. Read Cycle No.1 (Either Port Address Access)[6, 7, 8]Figure 4. R

CYDC128B16Document #: 001-01638 Rev. *H Page 2 of 29 Notes1. A0–A11 for 4k devices; A0–A12 for 8k devices; A0–A13 for 16k devices.2. BUSY is an outp

CYDC128B16Document #: 001-01638 Rev. *H Page 20 of 29Figure 6. Write Cycle No.1: R/W Controlled Timing[11, 12, 13, 14, 15, 16]Figure 7. Write Cycl

CYDC128B16Document #: 001-01638 Rev. *H Page 21 of 29Figure 8. Semaphore Read After Write Timing, Either Side[19, 20]Figure 9. Timing Diagram of S

CYDC128B16Document #: 001-01638 Rev. *H Page 22 of 29Figure 10. Timing Diagram of Read with BUSY (M/S=HIGH)[23]Figure 11. Write Timing with Busy I

CYDC128B16Document #: 001-01638 Rev. *H Page 23 of 29Figure 12. Busy Timing Diagram No.1 (CE Arbitration)Figure 13. Busy Timing Diagram No.2 (Addr

CYDC128B16Document #: 001-01638 Rev. *H Page 24 of 29Figure 14. Interrupt Timing DiagramsNotes25. tHA depends on which enable pin (CEL or R/WL) is

CYDC128B16Document #: 001-01638 Rev. *H Page 25 of 29Ordering Information Ordering Code Defintions8k x16 1.8V Asynchronous Dual-Port SRAMSpeed(ns)

CYDC128B16Document #: 001-01638 Rev. *H Page 26 of 29Package DiagramFigure 15. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A10051-85048 *E[+] Feedba

CYDC128B16Document #: 001-01638 Rev. *H Page 27 of 29AcronymsAcronym DescriptionCEchip enableCMOS complementary metal oxide semiconductorI/O input/o

CYDC128B16Document #: 001-01638 Rev. *H Page 28 of 29Document History PageDocument Title: CYDC128B16 1.8 V 4 K/8 K/16 K × 16 and 8 K/16 K × 8 ConsuM

Document #: 001-01638 Rev. *H Revised March 1, 2011 Page 29 of 29All products and company names mentioned in this document may be the trademarks of t

CYDC128B16Document #: 001-01638 Rev. *H Page 3 of 29ContentsFeatures ...

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CYDC128B16Document #: 001-01638 Rev. *H Page 4 of 29Pin ConfigurationsFigure 1. 100-Pin TQFP (Top View)[3]Notes3. Leave this pin unconnected. No tr

CYDC128B16Document #: 001-01638 Rev. *H Page 5 of 29Pin DefinitionsLeft Port Right Port DescriptionCELCERChip enableR/WLR/WRRead/write enableOELOERO

CYDC128B16Document #: 001-01638 Rev. *H Page 6 of 29Functional DescriptionThe CYDC128B16 is a low power complementary metal oxidesemiconductor (CMO

CYDC128B16Document #: 001-01638 Rev. *H Page 7 of 29Input Read RegisterThe Input Read Register (IRR) captures the status of twoexternal input device

CYDC128B16Document #: 001-01638 Rev. *H Page 8 of 29ArchitectureThe CYDC128B16 consists of an array of 4k, 8k, or 16k wordsof 16 dual-port RAM cell

CYDC128B16Document #: 001-01638 Rev. *H Page 9 of 29Table 3. Input Read Register Operation[1, 2]SFEN CE R/W OE UB LB ADDR I/O0–I/O1I/O2–I/O15ModeHL