Document Number: 001-52469 Rev. *H Page 27 of 50
AC Electrical Characteristics
AC Chip-Level Specifications
Tab le 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C T
A
85 °C, 3.0 V to 3.6 V and –40 °C T
A
85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 21. AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
F
IMO24
IMO frequency for 24 MHz 22.8
[13]
24 25.2
[13]
MHz Trimmed for 5 V or 3.3 V operation using factory
trim values. See Figure 6 on page 13. SLIMO
mode = 0.
F
IMO6
IMO frequency for 6 MHz 5.5
[13]
6 6.5
[13]
MHz Trimmed for 5 V or 3.3 V operation using factory
trim values. See Figure 6 on page 13. SLIMO
mode = 1.
F
CPU1
CPU frequency (5 V V
DD
nominal) 0.089
[13]
– 25.2
[13]
MHz Minimum CPU frequency is 0.022 MHz when
SLIMO mode = 0.
F
CPU2
CPU frequency (3.3 V V
DD
nominal)
0.089
[13]
– 12.6
[13]
MHz Minimum CPU frequency is 0.022 MHz when
SLIMO mode = 0.
F
BLK5
Digital PSoC block frequency (5 V
V
DD
nominal)
0 – 50.4
[13,14]
MHz Refer to AC Digital Block Specifications on
page 32.
F
BLK33
Digital PSoC block frequency (3.3
V V
DD
nominal)
0 – 25.2
[13,14]
MHz Refer to AC Digital Block Specifications on
page 32.
F
32K1
ILO frequency 15 32 64 kHz This specification applies when the ILO has
been trimmed.
F
32KU
ILO untrimmed frequency 5 – 100 kHz After a reset and before the M8C processor
starts to execute, the ILO is not trimmed.
F
32K2
External crystal oscillator – 32.76
8
– kHz Accuracy is capacitor and crystal dependent.
50% duty cycle.
F
PLL
PLL frequency – 23.98
6
– MHz Is a multiple (x732) of crystal frequency.
t
PLLSLEW
PLL lock time 0.5 – 10 ms Refer to Figure 7 on page 28.
t
PLLSLEWSLOW
PLL lock time for low gain setting 0.5 – 50 ms Refer to Figure 8 on page 28.
t
OS
External crystal oscillator startup to
1%
– 1700 2620 ms Refer to Figure 9 on page 28.
t
OSACC
External crystal oscillator startup to
100 ppm
– 2800 3800 ms The crystal oscillator frequency is within 100
ppm of its final value by the end of the t
OSACC
period. Correct operation assumes a properly
loaded 1 µW maximum drive level 32.768 kHz
crystal. 3.0 V V
DD
5.25 V, –40 C T
A
85 C.
t
XRST
External reset pulse width 10 – – s
DC24M 24 MHz duty cycle 40 50 60 %
DC
ILO
ILO duty cycle 20 50 80 %
Step24M 24 MHz trim step size – 50 – kHz
Fout48M 48 MHz output frequency 45.6
[13]
48.0 50.4
[13]
MHz Trimmed. Using factory trim values.
F
MAX
Maximum frequency of signal on
row input or row output.
– – 12.6
[13]
MHz
SR
POWERUP
Power supply slew rate – – 250 V/ms V
DD
slew rate during power up.
t
POWERUP
Time between end of POR state
and CPU code execution
– 16 100 ms Power up from 0 V.
t
JIT_IMO
[15]
24 MHz IMO cycle-to-cycle jitter
(RMS)
– 200 700 ps
24 MHz IMO long term N
cycle-to-cycle jitter (RMS)
– 300 900 ps N = 32
24 MHz IMO period jitter (RMS) – 100 400 ps
t
JIT_PLL
[15]
PLL cycle-to-cycle jitter (RMS) – 200 800 ps
PLL long term N cycle-to-cycle
jitter (RMS)
– 300 1200 ps N = 32
PLL period jitter (RMS) – 100 700 ps
Notes
13. Accuracy derived from IMO with appropriate trim for V
DD
range.
14. See the individual user module data sheets for information on maximum frequencies for user modules.
15. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
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