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9.16 Slave FIFO Asynchronous Address

Figure 9-17. Slave FIFO Asynchronous Address Timing Diagram

[24]

9.17 Sequence Diagram

9.17.1 Single and Burst Synchronous Read Example

Figure 9-18. Slave FIFO Synchronous Read Sequence and Timing Diagram

[24]

Figure 9-19. Slave FIFO Synchronous Sequence of Events Diagram

Table 31. Slave FIFO Asynchronous Address Parameters

[27]

Parameter Description Min Max Unit

SFA

FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time 10 – ns

FAH

RD/WR/PKTEND to FIFOADR[1:0] hold time 10 – ns

SLRD/SLWR/PKTEND

SLCS/FIFOADR [1:0]

SFA

FAH

IFCLK

SLRD

FLAGS

SLOE

DATA

SRD

RDH

OEon

XFD

XFLG

IFCLK

N+1

Data Driven: N

>= t

SRD

OEon

XFD

N+2

XFD

>= t

RDH

OEoff

N+4

N+3

OEoff

SFA

FAH

FIFOADR

SLCS

t=0

N+1

t=1

t=2

t=3

t=4

FAH

T=0

SFA

T=1

T=2

T=3

T=4

NNN+1 N+2

FIFO POINTER

N+3

FIFO DATA BUS

N+4

Not Driven Driven: N

SLOE

SLRD

N+1 N+2

N+3

Not Driven

SLRD

SLOE

IFCLK

IFCLK IFCLK IFCLK

N+4

IFCLK IFCLK

SLRD

N+1

SLRD

N+1

SLOE

Not Driven

N+4

IFCLK

SLOE

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 71 72

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