Cypress Semiconductor CY7C68016A Guia do Utilizador descarregar pdf (Página 46)

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Document Number: 38-08032 Rev. *X Page 46 of 71

9.1 Slave FIFO Synchronous Read

Figure 9-7. Slave FIFO Synchronous Read Timing Diagram

[24]

IFCLK

SLRD

FLAGS

SLOE

SRD

RDH

OEon

XFD

XFLG

DATA

IFCLK

N+1

OEoff

Table 19. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK

[25]

Parameter Description Min Max

Typ

Unit

Min Max

IFCLK

IFCLK period 20.83 – – – ns

SRD

SLRD to clock setup time 18.7 – – – ns

RDH

Clock to SLRD hold time 0 – – – ns

OEon

SLOE turn on to FIFO data valid – 10.5 – – ns

OEoff

SLOE turn off to FIFO data hold – 10.5 – – ns

XFLG

Clock to FLAGS output propagation delay – 9.5 – – ns

XFD

Clock to FIFO data output propagation delay – 11 – – ns

IFCLKR

IFCLK rise time – – – 900 ps

IFCLKF

IFCLK fall time – – – 900 ps

IFCLKOD

IFCLK output duty cycle – – 49 51 %

IFCLKJ

IFCLK jitter peak to peak – – – 300 ps

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