Cypress Semiconductor CY7C1386F Manual do Utilizador descarregar pdf (Página 25)

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document Number: 38-05545 Rev. *H Page 25 of 36

Switching Waveforms

Figure 5. Read Cycle Timing

[30]

CYC

CLK

ADSP

ADH

ADS

ADDRESS

ADSC

CEH

CES

GW, BWE,BW

Data Out (DQ)

High-Z

DOH

ADV

OEHZ

Single READ BURST READ

OEV

OELZ

CHZ

Burst wraps around

to its initial state

ADVH

ADVS

WEH

WES

ADH

ADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1)

Q(A2)

Q(A2 + 1)

Q(A3)

Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

ADV suspends burst

DON’T CARE

UNDEFINED

CLZ

Note

30.

Full width write can be initiated by either GW

LOW, or by GW HIGH, BWE LOW, and BW

LOW.

[+] Feedback

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 ... 35 36

DCD Sync SRAM 1
CY7C1387F (1 M × 18) 5
CY7C1386F (512 K × 36) 5
Single Read Accesses 8
Burst Sequences 9
Sleep Mode 9
(MODE = Floating or V 10
CY7C1386D, CY7C1386F 11
CY7C1387D, CY7C1387F 11
Disabling the JTAG Feature 13
Test Access Port (TAP) 13
Performing a TAP Reset 13
TAP Registers 13
TAP Instruction Set 13
Ordering Code Definitions 29
Units of Measure 33
Products 36
PSoC Solutions 36

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