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CY7C1365C

Document Number: 001-74584 Rev. *C Page 5 of 30

Pin Descriptions

Name I/O Description

, A

, A Input-

Synchronous

Address Inputs used to select one of the 256K address locations. Sampled at the rising edge of the

CLK if ADSP

or ADSC is active LOW, and CE

, and

are sampled active. A

[1:0]

feed the 2-bit

counter.

, BW

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.

Sampled on the rising edge of CLK.

GW Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write

is conducted (ALL bytes are written, regardless of the values on BW

[A:D]

and BWE).

BWE Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted

LOW to conduct a Byte Write.

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV

is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE

to select/deselect the device. ADSP is ignored

if CE

is HIGH.

is sampled only when a new

external address is loaded.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE

to select/deselect the device. CE

is sampled only when a new external address is loaded.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE

to select/deselect the device. CE

is assumed active throughout this document for BGA. CE

is sampled only when a new external address is loaded.

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,

the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data

pins. OE

is masked during the first clock of a Read cycle when emerging from a deselected state.

ADV

Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments

the address in a burst cycle.

ADSP Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A

[1:0]

are also loaded

into the burst counter. When ADSP

and ADSC are both asserted, only ADSP is recognized. ASDP is

ignored when

is deasserted HIGH.

ADSC

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A

[1:0]

are also loaded

into the burst counter. When ADSP

and ADSC are both asserted, only ADSP is recognized.

ZZ Input-

Asynchronous

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”

condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ

pin has an internal pull-down.

DQs I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the

addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled

by OE

. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a tri-state

condition.

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

DDQ

I/O Power

Supply

Power supply for the I/O circuitry.

SSQ

I/O Ground Ground for the I/O circuitry.

TDO JTAG serial

output

synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is

not being used, this pin should be left unconnected.

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