Cypress Semiconductor CY7C1365C Manual do Utilizador descarregar pdf (Página 24)

CY7C1365C

Document Number: 001-74584 Rev. *C Page 24 of 30

Figure 5. Read/Write Timing

[24, 25, 26]

Timing Diagrams (continued)

CYC

CLK

ADH

ADS

ADDRESS

CEH

CES

Single WRITE

D(A3)

A3 A4

BURST READBack-to-Back READs

High-Z

Q(A2)

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

WEH

WES

OEHZ

CDV

OELZ

A1 A5 A6

D(A5) D(A6)

Q(A1)

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

ADSP

ADSC

BWE, BW[A:D]

ADV

Data In (D)

Data Out (Q)

Notes

24. On this diagram, when CE

is LOW, CE

is HIGH and CE

is LOW. When CE is HIGH, CE

is HIGH or CE

is LOW or CE

is HIGH.

25. The data bus (Q) remains in High Z following a Write cycle unless an ADSP

, ADSC, or ADV cycle is performed.

26.

is HIGH.

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 30

9-Mbit (256 K × 32) 1
Flow-Through Sync SRAM 1
CY7C1365C 10
Disabling the JTAG Feature 11
Test Access Port (TAP) 11
Performing a TAP Reset 11
TAP Registers 11
TAP Instruction Set 12
Ordering Code Definitions 26
Units of Measure 28
Products 30
PSoC Solutions 30

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