CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
6
Pin Definitions (119-Ball BGA)
x18 Pin Locations x36 Pin Locations Name I/O Description
4P, 4N, 2A, 3A, 5A,
6A, 3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R, 2T,
3T, 5T, 6B, 6T
4P, 4N,
2A, 2C, 2R, 3A, 3B,
3C, 3T, 4T, 5A, 5B,
5C, 5T, 6A, 6B, 6C,
6R
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address
locations. Sampled at the rising edge of the CLK if
ADSP
or ADSC is active LOW, and CE
1
, CE
2
, and
CE
3
are sampled active. A
[1:0]
feed the 2-bit
counter.
5L, 3G 5L, 5G, 3G, 3L BW
a
BW
b
BW
c
BW
d
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with
BWE
to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
4M 4M GW Input-
Synchronous
Global Write Enable Input, active LOW. When as-
serted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regard-
less of the values on BW
a,b,c,d
and BWE).
4H 4H BWE Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on
the rising edge of CLK. This signal must be assert-
ed LOW to conduct a byte write.
4K 4K CLK Input-Clock Clock Input. Used to capture all synchronous inputs
to the device. Also used to increment the burst
counter when ADV
is asserted LOW, during a burst
operation.
4E 4E CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ig-
nored if CE
1
is HIGH.
97 97 CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and CE
3
to select/deselect the device. This pin is
also used for expansion to a 16M density SRAM.
92 92 CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and
CE
2
to select/deselect the device.
4F 4F OE Input-
Asynchronous
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input
data pins. OE
is masked during the first clock of a
read cycle when emerging from a deselected state.
4G 4G ADV Input-
Synchronous
Advance Input signal, sampled on the rising edge
of CLK. When asserted, it automatically increments
the address in a burst cycle.
4A 4A ADSP Input-
Synchronous
Address Strobe from Processor, sampled on the
rising edge of CLK. When asserted LOW, A is cap-
tured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP
and ADSC are
both asserted, only ADSP
is recognized. ASDP is
ignored when CE
1
is deasserted HIGH.
4B 4B ADSC Input-
Synchronous
Address Strobe from Controller, sampled on the ris-
ing edge of CLK. When asserted LOW, A
[x:0]
is cap-
tured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP
and ADSC are
both asserted, only ADSP
is recognized.
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