Cypress Semiconductor CY7C1364C Manual do Utilizador Página 22

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CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
22
Switching Characteristics
Over the Operating Range
[12, 13, 14]
-200 -166 -133 -100
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
CYC
Clock Cycle Time 5.0 6.0 7.5 10 ns
t
CH
Clock HIGH 1.6 1.7 1.9 3.2 ns
t
CL
Clock LOW 1.6 1.7 1.9 3.2 ns
t
AS
Address Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 ns
t
AH
Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
CO
Data Output Valid After CLK Rise 3.1 3.5 4.2 5.0 ns
t
DOH
Data Output Hold After CLK Rise 1.0 1.5 1.5 1.5 ns
t
ADS
ADSP, ADSC Set-Up Before CLK
Rise
1.5 1.5 2.0 2.0 ns
t
ADH
ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
WES
BWE, GW, BW
x
Set-Up Before CLK
Rise
1.5 1.5 2.0 2.0 ns
t
WEH
BWE, GW, BW
x
Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
ADVS
ADV Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 ns
t
ADVH
ADV Hold After CLK Rise 1.5 1.5 0.5 0.5 ns
t
DS
Data Input Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 ns
t
DH
Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
CES
ChipEnable Set-Up 1.5 1.5 2.0 2.0 ns
t
CEH
Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
CHZ
Clock to High-Z
[13]
1.5 3.1 1.5 3.5 1.5 4.2 1.5 5.0 ns
t
CLZ
Clock to Low-Z
[13]
0 0 0 0 ns
t
EOHZ
OE HIGH to Output High-Z
[13, 14]
3.2 3.5 4.2 4.5 ns
t
EOLZ
OE LOW to Output Low-Z
[13, 14]
0 0 0 0 ns
t
EOV
OE LOW to Output Valid
[13]
3.1 3.5 4.2 5.0 ns
Notes:
12. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified I
OL
/I
OH
and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
13. t
CHZ
, t
CLZ
, t
OEV
, t
EOLZ
, and t
EOHZ
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mV from
steady-state voltage.
14. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
.
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