Cypress Semiconductor STK14C88-5 Manual do Utilizador descarregar pdf (Página 11)

STK14C88-5

Document Number: 001-51038 Rev. *B Page 11 of 18

SRAM Write Cycle

Parameter

Description

35 ns 45 ns

Unit

Min Max Min Max

Cypress

Parameter

Alt

AVAV

Write cycle time 35 – 45 – ns

PWE

WLWH,

WLEH

Write pulse width 25 – 30 – ns

SCE

ELWH,

ELEH

Chip enable to end of write 25 – 30 – ns

DVWH,

DVEH

Data setup to end of write 12 – 15 – ns

WHDX,

EHDX

Data hold after end of write 0 – 0 – ns

AVWH,

AVEH

Address setup to end of write 25 – 30 – ns

AVWL,

AVEL

Address setup to start of write 0 – 0 – ns

WHAX,

EHAX

Address hold after end of write 0 – 0 – ns

HZWE

[13,14]

WLQZ

Write enable to output disable – 13 – 15 ns

LZWE

[13]

WHQX

Output active after end of write 5 – 5 – ns

Switching Waveforms

Figure 10. SRAM Write Cycle 1: WE Controlled

[15, 16]

Figure 11. SRAM Write Cycle 2: CE Controlled

[15, 16]

SCE

PWE

HZWE

LZWE

ADDRESS

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

ADDRESS

SCE

PWE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

13. Measured ±200 mV from steady state output voltage.

14. If WE

is Low when CE goes Low, the outputs remain in the high impedance state.

15. HSB

must be high during SRAM WRITE cycles.

16.

or WE must be greater than V

during address transitions.

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