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STK11C68

Document Number: 001-50638 Rev. *C Page 9 of 15

SRAM Write Cycle

Parameter

Description

25 ns 35 ns 45 ns

Unit

Min Max Min Max Min Max

Cypress

Parameter

Alt

AVAV

Write Cycle Time 25 35 45 ns

PWE

WLWH,

WLEH

Write Pulse Width 20 25 30 ns

SCE

ELWH,

ELEH

Chip Enable To End of Write 20 25 30 ns

DVWH,

DVEH

Data Setup to End of Write 10 12 15 ns

WHDX,

EHDX

Data Hold After End of Write 0 0 0 ns

AVWH,

AVEH

Address Setup to End of Write 20 25 30 ns

AVWL,

AVEL

Address Setup to Start of Write 0 0 0 ns

WHAX,

EHAX

Address Hold After End of Write 0 0 0 ns

HZWE

[6,7]

WLQZ

Write Enable to Output Disable 10 13 15 ns

LZWE

[6]

WHQX

Output Active After End of Write 5 5 5 ns

Switching Waveforms

Figure 7. SRAM Write Cycle 1: WE Controlled

[7, 8]

Figure 8. SRAM Write Cycle 2: CE and OE Controlled

[7, 8]

SCE

PWE

HZWE

LZWE

ADDRESS

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

ADDRESS

SCE

PWE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

7. If WE

is Low when CE goes Low, the outputs remain in the high impedance state.

or WE must be greater than V

during address transitions.

Not recommended for new designs.

In production to support ongoing production programs.

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