Cypress Semiconductor STK11C68-5 Manual do Utilizador descarregar pdf (Página 3)

STK11C68

Document Number: 001-50638 Rev. *C Page 3 of 15

Pin Configurations

Figure 1. Pin Diagram - 28-Pin SOIC/DIP and 28-Pin LLC

Pin Definitions

Pin Name Alt I/O Type Description

–A

Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

-DQ

Input or

Output

Bidirectional Data I/O Lines. Used as input or output lines depending on operation.

WE W

Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the

I/O pins is written to the specific address location.

Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the

chip.

Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers

during read cycles. Deasserting OE

HIGH causes the I/O pins to tristate.

Ground Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

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723

Not recommended for new designs.

In production to support ongoing production programs.

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