Cypress Semiconductor ISR 37000 CPLD Especificações descarregar pdf (Página 8)

Design Considerations for ISR Programming of Cypress CPLDs

to the manufacturing difficulty of fabricating traces with widely

varying impedance on the same board.

In lieu of this technique, it is recommended use the buffering

scheme described in the following section for best signal qual-

ity.

Adding Extra Buffering on the PCB

The best signal integrity for the clock line is achieved by incor-

porating buffering on the board as shown in Figure 11. This

buffering, with proper termination, can guard more effectively

against both of the transmission line effects previously de-

scribed. The buffer should be placed close to the 10-pin head-

er connector so that the termination resistor can match the

cable characteristic impedance and prevent reflection at the

buffer input. The on-board buffer can provide separate buffer-

ing for each ISR device clock line. The series resistor, placed

close to the buffer output, can match the characteristic imped-

ance of the trace on the board and prevent reflections at the

buffer output. In Figure 11 it is not crucial that the clock traces

have the same length for each device clock since there is no

danger of timing problems from one ISR device to the next.

This is because the data output from one ISR device does not

propagate to the next device until the falling edge of the clock

as defined in the IEEE 1149.1 specification.

An HC buffer such as the HC244 for 5V V

, or an LVT244

for 3.3V V

, is recommended for on-board buffering. These

are selected because they provide good drive capability and

input noise margin. An FC buffer should be avoided since the

faster edge rates will worsen transmission line effects. The

source termination resistor is selected to match the source

impedance to the characteristic impedance of the trace. In

this way, the output resistance of the buffer plus the source

termination resistor R

equals Z

. A carefully matched

source prevents voltage reflections towards the load. It is im-

portant to note that there is often no best value for R

due to

uneven impedances when driving high and low for logic fam-

ilies such as TTL. This trade-off can still produce acceptable

signal integrity.

Extra buffering with termination is recommended wherever

the impedance of the trace changes greatly, such as at the

connection between a PCB and an add-on card. If large num-

bers of ISR devices are required in the ISR programming

chain, the clock buffer outputs can feed a clock tree layout, or

can alternatively feed a daisy chain of cascaded ISR devices

(replacing source termination with end termination). This

combines the configuration shown in Figure 11 with one of

Figure 9 or Figure 8.

Valid ISR Programming Voltages

Only the Delta39K, Quantum38K, and PSI families of pro-

grammable devices support any choice of programming volt-

age on the ISR signals (V

CCJTAG

) from 3.3V, 2.5V, and 1.8V.

All are provided by the C3ISR programming cable. The rec-

ommended voltage is 3.3V, device permitting.

Ultra37000 and F

LASH

370i devices permit 5V and 3.3V levels

(with appropriate V

CCIO

level). The F

LASH

370i device family is

the only one that requires a 12V supervoltage on ISRen for

programming. To maintain compatibility, Ultra37000 devices

(except for Ultra37000V) are designed tolerant to 12V on the

equivalent JTAGen pin.

Figure 10. Clock Tree Trace Layout Implementation

ISR

device

ISR

device

ISR

device

ISR

device

TCK Buffer

Impractical:

Difficulty to fabricate

traces with widely

varying impedance

Figure 11. Buffering with Termination

HC244

R=33

Ω

R=33

Ω

R=33

Ω

R=33

Ω

R=33

Ω

R=33

Ω

R=33

Ω

R=33

Ω

ISR device

or group of devices

PCB

TCK

ISR

device

Cable Buffer

PCB

Source Termination

Ribbon Cable

Z=100

Ω

BEST

Layout

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 19 20

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