Cypress Semiconductor CY8C24894 Manual do Utilizador descarregar pdf (Página 37)

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Document Number: 38-12018 Rev. *Q Page 37 of 48

10.4.10 AC I

C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40

°C ≤ T

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T

≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Figure 10-6. Definition for Timing for Fast/Standard Mode on the I

C Bus

Table 10-27. AC Characteristics of the I

C SDA and SCL Pins for Vdd

Symbol Description

Standard Mode Fast Mode

Units Notes

Min Max Min Max

SCLI2C

SCL Clock Frequency 0 100 0 400 kHz

HDSTAI2C

Hold Time (repeated) START Condition. After

this period, the first clock pulse is generated.

4.0 –0.6– μs

LOWI2C

LOW Period of the SCL Clock 4.7 –1.3– μs

HIGHI2C

HIGH Period of the SCL Clock 4.0 –0.6– μs

SUSTAI2C

Setup Time for a Repeated START Condition 4.7 –0.6– μs

HDDATI2C

Data Hold Time 0 –0– μs

SUDATI2C

Data Setup Time 250 –100

[17]

–ns

SUSTOI2C

Setup Time for STOP Condition 4.0 –0.6– μs

BUFI2C

Bus Free Time Between a STOP and START

Condition

4.7 –1.3– μs

SPI2C

Pulse Width of spikes are suppressed by the

input filter.

– – 0 50 ns

SDA

SCL

Sr SP

BUFI2C

SPI2C

HDSTAI2C

SUSTOI2C

SUSTAI2C

LOWI2C

HIGHI2C

HDDATI2C

HDSTAI2C

SUDATI2C

Note

17. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

SU;DAT

Š 250 ns must then be met. This automatically is the case

if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line t

rmax

+ t

SU;DAT

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

[+] Feedback

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