Document Number: 001-53754 Rev. *F Page 31 of 50
AC Low Power Comparator Specifications
Tab le 21 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C T
A
85 °C, or 3.0 V to 3.6 V and –40 °C T
A
85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design
guidance only.
AC Digital Block Specifications
Tab le 22 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C T
A
85 °C, or 3.0 V to 3.6 V and –40 °C T
A
85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are
for design guidance only.
Table 21. AC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
t
RLPC
LPC response time – – 50 s 50 mV overdrive comparator
reference set within V
REFLPC
.
Table 22. AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
functions
Block input clock frequency
V
DD
4.75 V – – 49.92
[17]
MHz
V
DD
< 4.75 V – – 25.92
[17]
MHz
Timer Input clock frequency
No capture, V
DD
4.75 V – – 49.92
[17]
MHz
No capture, V
DD
< 4.75 V – – 25.92
[17]
MHz
With capture – – 25.92
[17]
MHz
Capture pulse width 50
[18]
––ns
Counter Input clock frequency
No enable input, V
DD
4.75 V – – 49.92
[17]
MHz
No enable input, V
DD
< 4.75 V – – 25.92
[17]
MHz
With enable input – – 25.92
[17]
MHz
Enable input pulse width 50
[18]
––ns
Dead
Band
Kill pulse width
Asynchronous restart mode 20 – – ns
Synchronous restart mode 50
[18]
––ns
Disable mode 50
[18]
––ns
Input clock frequency
V
DD
4.75 V – – 49.92
[17]
MHz
V
DD
< 4.75 V – – 25.92
[17]
MHz
CRCPRS
(PRS
Mode)
Input clock frequency
V
DD
4.75 V – – 49.92
[17]
MHz
V
DD
< 4.75 V – – 25.92
[17]
MHz
CRCPRS
(CRC
Mode)
Input clock frequency – – 25.92
[17]
MHz
SPIM Input clock frequency – – 8.64
[17]
MHz The SPI serial clock (SCLK)
frequency is equal to the input
clock frequency divided by 2.
SPIS Input clock (SCLK) frequency – – 4.32
[17]
MHz The input clock is the SPI SCLK in
SPIS mode.
Width of SS_Negated between transmissions 50
[18]
––ns
Trans-
mitter
Input Clock Frequency The baud rate is equal to the input
clock frequency divided by 8.
V
DD
4.75 V, 2 stop bits – – 49.92
[17]
MHz
V
DD
4.75 V, 1 stop bit – – 25.92
[17]
MHz
V
DD
< 4.75 V – – 25.92
[17]
MHz
Notes
17. Accuracy derived from IMO with appropriate trim for V
DD
range.
18. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
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