Cypress Semiconductor CY8C24894 Especificações descarregar pdf (Página 14)

CY8C24894

Document Number: 001-53754 Rev. *F Page 14 of 50

DC Electrical Characteristics

DC Chip Level Specifications

Tab le 5 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C

 T

 85 °C, or 3.0 V to 3.6 V and –40 °C  T

 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for

design guidance only.

Table 5. DC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

Supply voltage 3.0 – 5.25 V See DC POR and LVD specifications,

Table 15 on page 25.

DD5

Supply current, IMO = 24 MHz, V

= 5 V – 14 27 mA Conditions are V

= 5.0 V, T

= 25 C,

CPU = 3 MHz, 48 MHz disabled, VC1 =

1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75

kHz, Analog power = off.

DD3

Supply current, IMO = 24 MHz, V

= 3.3 V – 8 14 mA Conditions are V

= 3.3 V, T

= 25 C,

CPU = 3 MHz, 48 MHz disabled, VC1 =

1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367

kHz, Analog power = off.

Sleep

[5]

(mode) current with POR, LVD,

sleep timer, and WDT.

[6]

– 3 6.5 A Conditions are with ILO active, V

3.3 V, –40

C  T

 55 C, Analog

power = off.

SBH

Sleep (mode) current with POR, LVD, sleep

timer, and WDT at high temperature.

[6]

– 4 25 A Conditions are with ILO active, V

3.3 V, 55

C < T

 85 C, Analog power

= off.

Notes

5. Errata: When the device is operating at 4.75 V to 5.25 V and the 3.3 V regulator is enabled, a short low pulse may be created on the DP signal line during device

wake-up. The 15-20 μs low pulse of the DP line may be interpreted by the host computer as a deattach or the beginning of a wake-up. More details in “Errata” on page 46.

6. Standby current includes all functions (POR, LVD, WDT, sleep timer) needed for reliable system operation. This should be compared with devices that have similar

functions enabled.

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