CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
Document Number: 001-05809 Rev. *K Page 13 of 44
Additional Pin Descriptions
The following sections provide additional pin information.
DPLUS, DMINUS
DPLUS and DMINUS are the USB signaling pins; they must be
tied to the D+ and D– pins of the USB connector. Because they
operate at high frequencies, the USB signals require special
consideration when designing the layout of the PCB. See
General PCB Layout Recommendations for USB Mass Storage
Designs on page 40 for PCB layout recommendations.
When RESET# is released, the assertion of the internal pull up
on D+ is gated by a combination of the state of the
VBUS_ATA_ENABLE pin, the value of configuration address
0x08 bit 0 (DRVPWRVLD Enable), and the detection of a
non-removable ATA/ATAPI drive on the IDE bus. See Table 2 for
a description of this relationship.
SCL, SDA
The clock and data pins for the I
2
C port must be connected to
the configuration EEPROM and to 2.2K pull up resistors tied to
V
CC
. If no EEPROM is used in the design, the SCL and SDA pins
must still be connected to pull up resistors. The SCL and SDA
pins are active for several milliseconds at startup.
XTALIN, XTALOUT
The AT2LP requires a 24 MHz (
100 ppm) signal to derive
internal timing. Typically, a 24 MHz (12 pF, 500 W,
parallel-resonant, fundamental mode) crystal is used, but a
24 MHz square wave (3.3 V, 50/50 duty cycle) from another
source can also be used. If a crystal is used, connect its pins to
XTALIN and XTALOUT, and also through 12 pF capacitors to
GND as shown in Figure 6. If an alternate clock source is used,
apply it to XTALIN and leave XTALOUT unconnected.
Figure 6. XTALIN/XTALOUT Diagram
SYSIRQ
The SYSIRQ pin provides a way for systems to request service
from host software by using the USB interrupt pipe on endpoint
1 (EP1). If the AT2LP has no pending interrupt data to return,
USB interrupt pipe data requests are NAK’ed. If pending data is
available, the AT2LP returns 16 bits of data. This data indicates
whether AT2LP is operating in high speed or full speed, whether
the AT2LP is reporting self powered or bus powered operation,
and the states of any GPIO pins that are configured as inputs.
GPIO pins can be individually set as inputs or outputs, with byte
0x09 of the configuration data. The state of any GPIO pin that is
not set as an input is reported as ‘0’ in the EP1 data.
Table 3 gives the bitmap for the data returned on the interrupt
pipe and Figure 7 on page 14 depicts the latching algorithm
incorporated by the AT2LP.
The SYSIRQ pin must be pulled LOW if HID functionality is used.
Refer to HID Functions for Button Controls on page 15 for more
details on HID functionality.
Table 2. D+ Pull Up Assertion Dependencies
VBUS_ATA_EN111100
DRVPWRVLD Enable Bit110011
ATA/ATAPI Drive Detected
Yes No Yes No Yes No
State of D+ pull up111000
24MHz Xtal
12pF
XTALIN XTALOUT
12pF
Table 3. Interrupt Data Bitmap
EP1 Data Byte 1 EP1 Data Byte 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
USB High Speed
VBUS Powered
RESERVED
RESERVED
GPIO[5]
GPIO[4]
GPIO[3]
GPIO[2]
GPIO[1]
GPIO[0]
(24 páginas)
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