Cypress Semiconductor CY7C64013C Guia do Utilizador

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CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 9 of 49USB Device Address 0x10 R/W USB Device Address register 14-1EP0 Counter

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 10 of 499.0 ClockingThe chip can be clocked from either the internal on-chip c

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 11 of 49before the part executes code. See Section 10.1 for moredetails.1 = Dis

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 12 of 49The microcontroller begins execution from ROM address0x0000 after a LVR

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 13 of 4911.0 Suspend ModeThe CY7C637xxC parts support a versatile low-powersus

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 14 of 49 12.0 General Purpose I/O PortsPorts 0 and 1 provide up to 16 versatil

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 15 of 49Bit [7:0]: P0[7:0]1 = Port Pin is logic HIGH0 = Port Pin is logic LOWBi

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 16 of 4912.1 Auxiliary Input PortPort 2 serves as an auxiliary input port as sh

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 17 of 4913.2 USB Port Status and ControlUSB status and control is regulated by

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 18 of 4914.0 USB DeviceThe CY7C637xxC supports one USB Device Address withthre

enCoRe™ USB Combination Low-SpeedUSB and PS/2 Peripheral ControllerCY7C63722CCY7C63723CCY7C63743CCypress Semiconductor Corporation • 198 Champion C

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 19 of 49In addition, the Mode Bits are automatically changed by theSIE in respo

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 20 of 4915.0 USB Regulator OutputThe VREG pin provides a regulated output for

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 21 of 4917.0 Serial Peripheral Interface (SPI)SPI is a four-wire, full-duplex

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 22 of 49hardware provides 8 output clocks on the SCK pin (P0.7) foreach byte tr

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 23 of 4917.5 SPI InterruptFor SPI, an interrupt request is generated after a by

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 24 of 4918.0 12-bit Free-running TimerThe 12-bit timer operates with a 1-µs ti

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 25 of 4919.0 Timer Capture RegistersFour 8-bit capture timer registers provide

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 26 of 49Bit [7:4]: Reserved.Bit [3:0]: Capture A/B, Falling/Rising EventThese b

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 27 of 4920.0 Processor Status and Control RegisterBit 7: IRQ PendingWhen an in

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 28 of 49During a Watchdog Reset, the Processor Status and ControlRegister is se

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 2 of 492.0 Logic Block Diagram3.0 Functional Overview3.1 enCoRe USB—The New U

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 29 of 4921.3 Interrupt SourcesThe following sections provide details on the dif

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 30 of 49A USB bus reset is indicated by a single ended zero (SE0)on the USB D+

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 31 of 49Bit [7:0]: P0 [7:0] Interrupt Enable1 = Enables GPIO interrupts from th

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 32 of 49Bit [7:0]: P1[7:0] Interrupt Polarity1 = Rising GPIO edge0 = Falling GP

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 33 of 49Mode Column:The 'Mode' column contains the mnemonic names giv

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 34 of 49The response of the SIE can be summarized as follows:1. The SIE will on

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 35 of 49Control ReadACK IN/Status OUT1 1 1 1 OUT 2 UC valid 1 1 updates UC UC 1

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 36 of 491 1 0 0 OUT x UC x UC UC UC UC UC UC UC NoChange Ignore no1 1 0 0 IN x

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 37 of 4923.0 Register SummaryAddress Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bi

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 38 of 4924.0 Absolute Maximum RatingsStorage Temperature ...

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 3 of 49event, and subtracting the two values. The four capture timerssave a pro

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 39 of 49Note:11. The 200Ω internal resistance at the VREG pin gives a standard

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 40 of 49 26.0 Switching CharacteristicsParameter Description Conditions Min. M

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 41 of 49TSCKHSPI Clock High Time High for CPOL = 0, Low for CPOL = 1 125 nsTSCK

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 42 of 49 Figure 26-3. Receiver Jitter ToleranceFigure 26-4. Differential to EOP

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 43 of 49 Figure 26-6. SPI Master Timing, CPHA = 0MSBTMSULSBTMHDTSCKHTMDOSSSCK (

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 44 of 49 MSBTMSULSBTMHDTSCKHTMDO1SSSCK (CPOL=0)SCK (CPOL=1)MOSIMISO(SS is under

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 45 of 49 27.0 Ordering InformationOrdering Code EPROM SizePackageNamePackage

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 46 of 4928.0 Package Diagrams (continued)PIN 1 IDSEATING PLANE0.597[15.163]0.6

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 47 of 4928.0 Package Diagrams (continued)24-Lead Quarter Size Outline Q1351-85

CY7C63722CCY7C63723CCY7C63743CDocument #: 38-08022 Rev. *C Page 48 of 49© Cypress Semiconductor Corporation, 2004. The information contained herein is

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 4 of 496.0 Programming ModelRefer to the CYASM Assembler User’s Guide for more

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 49 of 49Document History PageDocument Title: CY7C63722C, CY7C63723C, CY7C63743C

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 5 of 49• DSPINIT: EQU 30h• MOV A,DSPINIT6.6.2 Direct“Direct” address mode is us

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 6 of 49MOV A,[expr] direct 1A 5CPL 3A 4MOV A,[X+expr] index 1B 6ASL 3B 4MOV

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 7 of 498.0 Memory Organization8.1 Program Memory Organization[1] After reset A

CY7C63722CCY7C63723CCY7C63743CFOR FORDocument #: 38-08022 Rev. *C Page 8 of 498.2 Data Memory OrganizationThe CY7C637xxC microcontrollers provide 256