Cypress Semiconductor CY7C1364C Manual do Utilizador descarregar pdf (Página 11)

CY7C1364C

Document Number: 001-74592 Rev. *B Page 11 of 29

The TAP controller used in this SRAM is not fully compliant to the

1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented.

The TAP controller cannot be used to load address data or

control signals into the SRAM and cannot preload the I/O buffers.

The SRAM does not implement the 1149.1 commands EXTEST

or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;

rather, it performs a capture of the I/O ring when these

instructions are executed.

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO balls. To execute

the instruction once it is shifted in, the TAP controller needs to be

moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all 0s.

EXTEST is not implemented in this SRAM TAP controller, and

therefore this device is not compliant to 1149.1. The TAP

controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction

instruction has been loaded. There is one difference between the

two instructions. Unlike the SAMPLE/PRELOAD instruction,

EXTEST places the SRAM outputs in a high Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register

upon power up or whenever the TAP controller is given a test

logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to

be connected between the TDI and TDO balls when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a high Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because there

is a large difference in the clock frequencies, it is possible that

during the Capture-DR state, an input or output will undergo a

transition. The TAP may then try to capture a signal while in

transition (metastable state). This will not harm the device, but

there is no guarantee as to the value that will be captured.

Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture setup plus hold

times (t

and t

). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an issue, it is

still possible to capture all other signals and simply ignore the

value of the CK and CK

captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

PRELOAD enables an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells prior

to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required – that is, while data captured

is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO balls. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 29 30

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