Cypress Semiconductor CY7C1363C Manual do Utilizador

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CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 9 of 31Functional OverviewAll synchronous inputs pass through input registers controlledby the ri

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 10 of 31ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min. Max. UnitIDD

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 11 of 31Partial Truth Table for Read/Write[3, 8]Function (CY7C1361C) GW BWE BWDBWCBWBBWARead H H

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 12 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1361C/CY7C1363C incorporates a serial boun

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 13 of 31TDI and TDO balls as shown in the Tap Controller BlockDiagram. Upon power-up, the instruc

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 14 of 31PRELOAD allows an initial data pattern to be placed at thelatched parallel outputs of the

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 15 of 313.3V TAP AC Test ConditionsInput pulse levels ...

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 16 of 31Scan Register SizesRegister Name Bit Size (x 36) Bit Size (x 18)Instruction 3 3Bypass 1 1

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 17 of 31119-Ball BGA Boundary Scan Order CY7C1361C (256K x 36) CY7C1363C (512K x 18)Bit # ball ID

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 18 of 31165-Ball FBGA Boundary Scan Order CY7C1361C (256K x 36) CY7C1363C (512K x 18)Bit # ball

9-Mbit (256K x 36/512K x 18) Flow-Through SRAMCY7C1361CCY7C1363CCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 40

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 19 of 31Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not te

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 20 of 31Capacitance[15]Parameter Description Test Conditions100 TQFPMax.119 BGAMax.165 FBGA Max.

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 21 of 31Switching Characteristics Over the Operating Range[20, 21]Parameter Description–133 –100

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 22 of 31Timing DiagramsRead Cycle Timing[22]Note: 22. On this diagram, when CE is LOW: CE1 is LOW

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 23 of 31Write Cycle Timing[22, 23]Note: 23.Full width write can be initiated by either GW LOW; or

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 24 of 31Read/Write Cycle Timing[22, 24, 25]Notes: 24. The data bus (Q) remains in high-Z followin

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 25 of 31ZZ Mode Timing[26, 27]Notes: 26. Device must be deselected when entering ZZ mode. See Cyc

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 26 of 31Ordering InformationNot all of the speed, package and temperature ranges are available. P

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 27 of 31100 CY7C1361C-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 28 of 31Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES NOT INCLUDE MO

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 2 of 31 ADDRESSREGISTERBURSTCOUNTERAND LOGICCLRQ1Q0ENABLEREGISTERSENSEAMPSOUTPUTBUFFERSINPUTREGIS

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 29 of 31Package Diagrams (continued)1.2720.322165437LEABDCHGFKJUPNMTR12.0019.5030° TYP.2.40 MAX.A

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 30 of 31© Cypress Semiconductor Corporation, 2006. The information contained herein is subject t

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 31 of 31Document History PageDocument Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flo

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 3 of 31Pin Configurations AAAAA1A0NCNCVSSVDDNCAAAAAAAADQPBDQBDQBVDDQVSSQDQBDQBDQBDQBVSSQVDDQDQBDQ

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 4 of 31Pin Configurations (continued)AAAAA1A0NCNCVSSVDDNCNCAAAAAAADQPBDQBDQBVDDQVSSQDQBDQBDQBDQB

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 5 of 31Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/288MNC/144MDQPCDQCDQDDQCDQDA

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 6 of 31Pin Configurations (continued)165-Ball FBGA Pinout (3 Chip Enable)CY7C1361C (256K x 36)23

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 7 of 31Pin DefinitionsName I/O DescriptionA0, A1, A Input-SynchronousAddress Inputs used to selec

CY7C1361CCY7C1363CDocument #: 38-05541 Rev. *F Page 8 of 31VSSGround Ground for the core of the device. VSSQI/O Ground Ground for the I/O circuitry.