Document Number: 38-05537 Rev. *M Page 22 of 33
Switching Characteristics
Over the Operating Range
Parameter
[20, 21]
Description
-250 -200 -166
Unit
Min Max Min Max Min Max
t
Power
[22]
V
CC
(typical) to the first access read or
write
1–1–1–ms
Clock
t
CYC
Clock cycle time 4.0–5–6–ns
F
MAX
Maximum operating frequency – 250 – 200 – 166 MHz
t
CH
Clock HIGH 1.8 – 2.0 – 2.4 – ns
t
CL
Clock LOW 1.8 – 2.0 – 2.4 – ns
Output Times
t
CO
Data output valid after CLK rise – 2.8 – 3.2 – 3.5 ns
t
EOV
OE LOW to output valid – 2.8 – 3.2 – 3.5 ns
t
DOH
Data output hold after CLK rise 1.25 – 1.5 – 1.5 – ns
t
CHZ
Clock to high Z
[23, 24, 25]
1.25 2.8 1.5 3.2 1.5 3.5 ns
t
CLZ
Clock to low Z
[23, 24, 25]
1.25 – 1.5 – 1.5 – ns
t
EOHZ
OE
HIGH to output high Z
[23, 24, 25]
– 2.8 – 3.2 – 3.5 ns
t
EOLZ
OE LOW to output low Z
[23, 24, 25]
0–0–0–ns
Set-up Times
t
AS
Address set-up before CLK rise 1.4 – 1.5 – 1.5 – ns
t
DS
Data input set-up before CLK rise 1.4 – 1.5 – 1.5 – ns
t
CENS
CEN set-up before CLK rise 1.4 – 1.5 – 1.5 – ns
t
WES
WE, BW
x
set-up before CLK rise 1.4 – 1.5 – 1.5 – ns
t
ALS
ADV/LD set-up before CLK rise 1.4 – 1.5 – 1.5 – ns
t
CES
Chip select set-up 1.4 – 1.5 – 1.5 – ns
Hold Times
t
AH
Address hold after CLK rise 0.4 – 0.5 – 0.5 – ns
t
DH
Data input hold after CLK rise 0.4 – 0.5 – 0.5 – ns
t
CENH
CEN hold after CLK rise 0.4 – 0.5 – 0.5 – ns
t
WEH
WE, BW
x
hold after CLK rise 0.4–0.5–0.5–ns
t
ALH
ADV/LD hold after CLK rise 0.4 – 0.5 – 0.5 – ns
t
CEH
Chip select hold after CLK rise 0.4 – 0.5 – 0.5 – ns
Notes
20. Timing reference level is when V
DDQ
= 2.5 V.
21. Test conditions shown in (a) of Figure 4 on page 21 unless otherwise noted.
22. This part has a voltage regulator internally; t
power
is the time power needs to be supplied above V
DD
minimum initially, before a Read or Write operation can be initiated.
23. t
CHZ
, t
CLZ
, t
EOLZ
, and t
EOHZ
are specified with AC test conditions shown in (b) of Figure 4 on page 21. Transition is measured ± 200 mV from steady-state voltage.
24. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
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