Cypress Semiconductor CY7C0430CV Manual do Utilizador descarregar pdf (Página 10)

CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 10 of 37

Switching Characteristics Over the Industrial Operating Range

[6]

Parameter Description

CY7C0430BV and CY7C0430CV

Unit

–133 –100

Min. Max. Min. Max.

MAX2

[7]

Maximum Frequency 133 100 MHz

CYC2

[7]

Clock Cycle Time 7.5 10 ns

CH2

Clock HIGH Time 3 4 ns

CL2

Clock LOW Time 3 4 ns

Clock Rise Time 2 3 ns

Clock Fall Time 2 3 ns

Address Set-up Time 2.3 3 ns

Address Hold Time 0.7 0.7 ns

Chip Enable Set-up Time 2.3 3 ns

Chip Enable Hold Time 0.7 0.7 ns

R/W Set-up Time 2.3 3 ns

R/W Hold Time 0.7 0.7 ns

Input Data Set-up Time 2.3 3 ns

Input Data Hold Time 0.7 0.7 ns

Byte Set-up Time 2.3 3 ns

Byte Hold Time 0.7 0.7 ns

SCLD

CNTLD Set-up Time 2.3 3 ns

HCLD

CNTLD Hold Time 0.7 0.7 ns

SCINC

CNTINC Set-up Time 2.3 3 ns

HCINC

CNTINC Hold Time 0.7 0.7 ns

SCRST

CNTRST Set-up Time 2.3 3 ns

HCRST

CNTRST Hold Time 0.7 0.7 ns

SCRD

CNTRD Set-up Time 2.3 3 ns

HCRD

CNTRD Hold Time 0.7 0.7 ns

SMLD

MKLD Set-up Time 2.3 3 ns

HMLD

MKLD Hold Time 0.7 0.7 ns

SMRD

MKRD Set-up Time 2.3 3 ns

HMRD

MKRD Hold Time 0.7 0.7 ns

Output Enable to Data Valid 6.5 8 ns

OLZ

[8]

OE to Low-Z 1 1 ns

OHZ

[8]

OE to High-Z 1 6 1 7 ns

CD2

Clock to Data Valid 4.2 5 ns

CA2

Clock to Counter Address Readback Valid 4.7 5 ns

CM2

Clock to Mask Register Readback Valid 4.7 5 ns

Data Output Hold After Clock HIGH 1 1 ns

CKHZ

[9]

Clock HIGH to Output High-Z 1 4.8 1 6.8 ns

Notes:

6. If data is simultaneously written and read to the same address location and t

CCS

is violated, the data read from the address, as well as the subsequent data

remaining in the address is undefined.

7. f

MAX2

for commercial is 135 MHz. t

CYC2

Min. for commercial is 7.4 ns.

8. This parameter is guaranteed by design, but it is not production tested.

9. Valid for both address and data outputs.

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 37 38

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