Cypress Semiconductor MoBL CY62157EV30 Manual do Utilizador descarregar pdf (Página 9)

CY62157EV30 MoBL

Document #: 38-05445 Rev. *H Page 9 of 17

Figure 8 shows WE Controlled write cycle waveforms.

[23, 24, 25]

Figure 8. Write Cycle No. 1

Figure 9 shows CE

or CE

Controlled write cycle waveforms.

[23, 24, 25]

Figure 9. Write Cycle No. 1

Switching Waveforms (continued)

PWE

SCE

HZOE

VALID DATA

NOTE 26

ADDRESS

DATA I/O

BHE/BLE

PWE

SCE

HZOE

VALID DATA

NOTE 26

ADDRESS

DATA I/O

BHE/BLE

Notes

23. The internal write time of the memory is defined by the overlap of WE

, CE

= V

, BHE, BLE or both = V

, and CE

= V

. All signals must be active to initiate a

write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that

terminates the write.

24. Data I/O is high impedance if OE

= V

25. If CE

goes HIGH and CE

goes LOW simultaneously with WE = V

, the output remains in a high impedance state.

26. During this period, the I/Os are in output state. Do not apply input signals.

[+] Feedback

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