Cypress Semiconductor CY7C1425JV18 Manual do Utilizador descarregar pdf (Página 19)

CY7C1410JV18, CY7C1425JV18

CY7C1412JV18, CY7C1414JV18

Document #: 001-12561 Rev. *F Page 19 of 26

Power Up Sequence in QDR-II SRAM

Power up and initialize QDR-II SRAMs in a predefined manner

to prevent undefined operations.

Power Up Sequence

■

Apply power and drive DOFF either HIGH or LOW (All other

inputs can be HIGH or LOW).

❐

Apply V

before V

DDQ

❐

Apply V

DDQ

before V

REF

or at the same time as V

REF

❐

Drive DOFF HIGH.

■

Provide stable DOFF (HIGH), power and clock (K, K) for 1024

cycles to lock the DLL.

DLL Constraints

■

DLL uses K clock as its synchronizing input. The input has low

phase jitter, which is specified as t

KC Var

■

The DLL functions at frequencies down to 120 MHz.

■

If the input clock is unstable and the DLL is enabled, then the

DLL may lock onto an incorrect frequency, causing unstable

SRAM behavior. To avoid this, provide1024 cycles stable clock

to relock to the desired clock frequency.

Figure 3. Power Up Waveforms

> 1024 Stable clock

Start Normal

Operation

DOFF

Stable (< +/- 0.1V DC per 50ns )

Fix High (or tie to V

DDQ

)

DDQDD

Clock Start

(Clock Starts after Stable)

DDQ

Unstable Clock

[+] Feedback

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