Cypress Semiconductor CY7C1410AV18 Manual do Utilizador descarregar pdf (Página 3)

CY7C1410AV18

CY7C1425AV18

CY7C1412AV18

CY7C1414AV18

Document #: 38-05615 Rev. *C Page 3 of 25

Logic Block Diagram (CY7C1412AV18)

CLK

A

(19:0)

Gen.

K

K

Control

Logic

Address

Register

D

[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Q

[17:0]

Control

Logic

Address

Register

Reg.

Reg.

Reg.

18

20

18

36

18

BWS

[1:0]

V

REF

Write Add. Decode

18

A

(19:0)

20

C

C

18

1M x 18 Array

1M x 18 Array

Write

Reg

Write

Reg

CQ

CQ

18

DOFF

Logic Block Diagram (CY7C1414AV18)

CLK

A

(18:0)

Gen.

K

K

Control

Logic

Address

Register

D

[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Q

[35:0]

Control

Logic

Address

Register

Reg.

Reg.

Reg.

36

19

36

72

36

BWS

[3:0]

V

REF

Write Add. Decode

36

A

(18:0)

19

C

C

36

512K x 36 Array

512K x 36 Array

Write

Reg

Write

Reg

CQ

CQ

36

DOFF

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