Cypress Semiconductor CY7C1297H Manual do Utilizador descarregar pdf (Página 12)

CY7C1297H

Document #: 38-05669 Rev. *B Page 12 of 15

Read/Write Timing

[16, 18, 19]

Notes:

18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP

, ADSC, or ADV cycle is performed.

19. GW

is HIGH.

Timing Diagrams (continued)

CYC

CLK

ADH

ADS

ADDRESS

CEH

CES

Single WRITE

D(A3)

A3 A4

BURST READBack-to-Back READs

High-Z

Q(A2)

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

WEH

WES

OEHZ

CDV

OELZ

A1 A5 A6

D(A5) D(A6)

Q(A1)

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

ADSP

ADSC

BWE, BW[A:B]

ADV

Data In (D)

Data Out (Q)

[+] Feedback

1 2 ... 7 8 9 10 11 12 13 14 15

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