Cypress Semiconductor Z9973 Manual do Utilizador

3.3V, 125-MHz, Multi-Output Zero Delay BufferZ9973Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600Do

Z9973Document #: 38-07089 Rev. *D Page 2 of 9Pin Description [2]Pin Number Pin Name PWR I/O Type Pin Description11 PECL_CLK I PU PECL Clock Input.12

Z9973Document #: 38-07089 Rev. *D Page 3 of 9Functional DescriptionThe Z9973 has an integrated PLL that provides low-skew andlow-jitter clock outputs

Z9973Document #: 38-07089 Rev. *D Page 4 of 9SYNCQCQASYNCQCQASYNCQAQCSYNCQCQASYNCQAQCSYNCQCQASYNCQCQAVCO1:1 Mode2:1 Mode3:1 Mode3:2 Mode4:1 Mode4:3 M

Z9973Document #: 38-07089 Rev. *D Page 5 of 9Power ManagementThe individual output enable/freeze control of the Z9973allows the user to implement uni

Z9973Document #: 38-07089 Rev. *D Page 6 of 9Maximum Ratings[3]Maximum Input Voltage Relative to VSS: ... VSS – 0.3VMaximum Input Voltage R

Z9973Document #: 38-07089 Rev. *D Page 7 of 9Notes:7. 50Ω transmission line terminated into VDD/2.8. Tpd is specified for a 50-MHz input reference. T

Z9973Document #: 38-07089 Rev. *D Page 8 of 9© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without

Z9973Document #: 38-07089 Rev. *D Page 9 of 9Document Title: Z9973 3.3V, 125 MHz Multi-Output Zero Delay BufferDocument Number: 38-07089Rev. ECN No.