Cypress Semiconductor CY7C1410AV18 Manual do Utilizador descarregar pdf (Página 2)

CY7C1410AV18

CY7C1425AV18

CY7C1412AV18

CY7C1414AV18

Document #: 38-05615 Rev. *C Page 2 of 25

Logic Block Diagram (CY7C1410AV18)

CLK

A

(20:0)

Gen.

K

K

Control

Logic

Address

Register

D

[7:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Q

[7:0]

Control

Logic

Address

Register

Reg.

Reg.

Reg.

8

21

8

16

8

NWS

[1:0]

V

REF

Write Add. Decode

8

A

(20:0)

21

C

C

8

2M x 8 Array

2M x 8 Array

Write

Reg

Write

Reg

CQ

CQ

8

DOFF

Logic Block Diagram (CY7C1425AV18)

CLK

A

(20:0)

Gen.

K

K

Control

Logic

Address

Register

D

[8:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Q

[8:0]

Control

Logic

Address

Register

Reg.

Reg.

Reg.

9

21

9

18

9

BWS

[0]

V

REF

Write Add. Decode

9

A

(20:0)

21

C

C

9

2M x 9 Array

2M x 9 Array

Write

Reg

Write

Reg

CQ

CQ

9

DOFF

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