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Cypress Semiconductor enCoRe CY7C64215 Manual do Utilizador Página 9

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CY7C64215
Document Number: 38-08036 Rev. *E Page 9 of 33
28-Pin Part Pinout
The CY7C64215 enCoRe III device is available in a 28-pin package which is listed and illustrated in the following table. Every port pin
(labeled with a “P”) is capable of Digital I/O. However, Vss and Vdd are not capable of Digital I/O.
Table 3. 28-Pin Part Pinout (SSOP)
Pin
No.
Type
Name Description
Figure 4. CY7C64215 28-Pin enCoRe III Device
Digital Analog
1 Power GND Ground Connection.
2 I/O I, M P0[7] Analog Column Mux Input.
3 I/O I/O,M P0[5] Analog Column Mux Input and Column Output.
4 I/O I/O,M P0[3] Analog Column Mux Input and Column Output.
5 I/O I,M P0[1] Analog Column Mux Input.
6 I/O M P2[5]
7 I/O M P2[3] Direct Switched Capacitor Block Input.
8 I/O M P2[1] Direct Switched Capacitor Block Input.
9 I/O M P1[7] I2C Serial Clock (SCL).
10 I/O M P1[5] I2C Serial Data (SDA).
11 I/O M P1[3]
12 I/O M P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
13 Power GND Ground Connection.
14 USB D+
15 USB D-
16 Power Vdd Supply Voltage.
17 I/O M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
18 I/O M P1[2]
19 I/O M P1[4]
20 I/O M P1[6]
21 I/O M P2[0] Direct Switched Capacitor Block Input.
22 I/O M P2[2] Direct Switched Capacitor Block Input.
23 I/O M P2[4] External Analog Ground (AGND) Input.
24 I/O M P0[0] Analog Column Mux Input.
25 I/O M P0[2] Analog Column Mux Input and Column Output.
26 I/O M P0[4] Analog Column Mux Input and Column Output.
27 I/O M P0[6] Analog Column Mux Input.
28 Power Vdd Supply Voltage.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[4]
P2[2], AI
P2[0], AI
P1[6]
P1[4]
P1[2]
P1[0], I2C SDA
Vdd
D-
Vss
AI, P0[7]
AIO, P0 [5 ]
AIO, P0 [3 ]
AI, P0[1]
P2[5]
AI, P2[3]
AI, P2[1]
I2C SCL, P1[7]
I2 C SDA, P1 [5 ]
P1[3]
I2C SCL, P1[1]
Vss
D+
[+] Feedback
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